1. Field of the Invention
This invention relates generally to fabricating an interconnect for a semiconductor device and more particularly to the fabrication of a conductive plug having a large landing pad for a semiconductor device.
2. Description of the Prior Art
In the quest to achieve microminiaturization of integrated circuit devices, individual elements have been made very small and the elements have been closely packed. As devices are scaled down in dimension, there is a continuous challenge to produce smaller high density capacitors and connections to the substrate using a minimum number of process steps. For example in the recent past, integrated circuits with half a million transistors were produced with 2 micron line widths. Now, it is not uncommon to produce integrated circuits with several million transistors. As a result, conductive line widths were reduced to below 0.5 microns to attempt to maintain the overall size of integrate circuit chip. In the future, denser circuits will require that these line widths and connections must be made even smaller.
This miniaturization creates problems in photolithography alignment and in forming contacts to the substrate. Generally in the manufacturing of a (e.g., DRAM) cell of a highly integrated semiconductor device, making a storage electrode contact with a silicon substrate is a difficult process because of the precise alignment requirements of the various photolithography masks. Integrated circuit manufacturers have more difficulty aligning one feature to another and controlling tolerances as line widths decrease. For example, the alignment of the base of the bottom electrode (i.e., the plug) to the overlaying metal layer or cylindrical electrode (bottom electrode) is critical. The alignment tolerances should be increased to reduce misalignment errors and yield losses.
Others in the field have striven to solve other problems with interconnections. For example, U.S. Pat. No. 5,374,591 (Haswgawa et al.) shows a method of forming a metal plug where the adhesion layer around the via hole is removed. U.S. Pat. No. 5,459,100(Choi) shows a method of forming metal plugs in different depth holes. The patent uses two different oxide layers and etches a portion of the top oxide layer away. U.S. Pat. No. 5,567,270 (Liu) shows a method of forming plug contact with a larger top portion.
However, there is still a need for an efficient method to form a plug with a large top landing pad area.